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STLC60134S
TOSCATM INTEGRATED ADSL CMOS ANALOG FRONT-END CIRCUIT
FULLY INTEGRATED AFE FOR ADSL OVERALL 12 BIT RESOLUTION, 1.1MHz SIGNAL BANDWIDTH 8.8MS/s ADC 8.8MS/s DAC THD: -60dB @FULL SCALE 4-BIT DIGITAL INTERFACE TO/FROM THE DMT MODEM 1V FULL SCALE INPUT DIFFERENTIAL ANALOG I/O ACCURATE CONTINUOUS-TIME CHANNEL FILTERING 3rd & 4th ORDER TUNABLE CONTINUOUS TIME LP FILTERS 0.5 WATT AT 3.3V 0.5m HCMOS5 LA TECHNOLOGY 64 PIN TQFP PACKAGE DESCRIPTION STLC60134S is the Analog Front End of the STMicroelectronics ToscaTM ADSL chipset and when coupled with STLC60135 (DTM modem) alFigure 1. Block Diagram
TQFP64 ORDERING NUMBER: STLC60134S
lows to get a T1.413 Issue 2 compliant solution. The STLC60134S analog front end handles 2 transmission channels on a balanced 2 wire interconnection; a 16 to 640Kbit/s upstream channel and a 1.536 to 8.192Mbit/s downstream channel. A 256 carrier DMT coding (frequency spacing 4.3125kHz) transforms the downstream channel to a 1MHz bandwidth analog signal (tones 32255) and the upstream channel (tones 8-31) to a 100kHz bandwidth signal on the line. This asymmetrical data transmission system uses high resolution, high speed analog to digital and digital to analog conversion and high order analog filtering to reduce the echo and noise in both
R-MOS-C TUNING
I/V-REF
XTAL-DRIVER VCXO DAC
ADC G=-15...0dB step=1dB -+ + -
ERROR CORRECTION 13 bits
TXP TXN
ANALOG LOOP MUX 1.1MHz 1.1MHz 138KHz 4 bits DIGITAL IF DIGITAL LOOP
AGCtx
HC2
HC1
SC2
G=0..31dB step=1dB + -+ RXP(0:1) RXN(0:1)
DAC
12 bits
MUX
4 bits
AGCrx
D99TL453
August 1999
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STLC60134S
the ATU-C/ATU-R receivers and transmitters. External low noise driver and input stage used with STLC60134S guarantee low noise performances. The STLC60134S chip can be used at ATU-C and ATU-R ends (behaviour set by LTNT pin). The selection consists mainly of a filter interchange between the RX and TX path. The filters (with a programmable cutoff frequency) use automatic Continuous Time Tuning to avoid time varying phase characteristic which can be of dramatic consequence for DMT modem. It requires few external components, uses a 3.3V supply (a separate 3.0V supply of the digital part is possible) and is packaged in a 64-pin TQFP in order to reduce PCB area. The Receiver (RX) part The DMT signal coming from the line to the STLC60134S is first filtered by the two following external filters:
POTS HP filter: Attenuation of speech and POTS signalling Channel filter: Attenuation of echo signal to improve RX dynamic
pendent frequency pulling. The DAC which is driven by the CTRLIN pin provides a current output with 8-bit resolution and can be used to tune the XTAL frequency with the help of external components. A time constant between DAC input and VCXO output can be introduced (via the CTLIN interface) and programmed with the help of an external capacitor (on VCOC pin). See chapter 'VCXO' for the external circuit related to the VCXO. The Digital Interface part The digital part of the STLC60134S can be divided in 3 sections: The data interface converts the multiplexed data from/to the DMT signal processor into valid representation for the TX DAC and RX ADC. It performs also the error correction mechanism needed at the (redundant) ADC output. The control interface allows the board processor to configure the STLC60134S paths (RX/TX gains, filter band, ...) or settings (OSR, vcodac enable, digital / analog loopback,...). The test interface to enable digital (Full Scan, nandtree, loop backs, functional,...) or analog (TIN, TOUT assignation) tests to be performed. DMT Signal A DMT signal is basically the sum of N independently QAM modulated signals, each carried over a distinct carrier. The frequency separation of each carrier is 4.3125kHz with a total number of 256 carriers (ANSI). For N large, the signal can be modelled by a gaussian process with a certain amplitude probability density function. Since the maximum amplitude is expected to arise very rarely, we decide to clip the signal and to tradeoff the resulting SNR loss against AD/DA dynamic. A clipping factor (Vpeak/Vrms = "crest factor") of 5 will be used resulting in a maximum SNR of 75dB. ADSL DMT signals are nominally sent at -40dBm/Hz 3dB (-3.65dBm/carrier) with a maximal power of 100mW for down link transmitter and 15.7mW for uplink transmitter. DMT symbols are transmitted without 'windowing' causing sin (x)/x like sidelobes. For spectral response shaping, the 1st sidelobe level is assumed to be 13dB under the carrier level with an attenuation of -20dB/dec. The minimum SNR + D neede d for DMT carrier demodulation is about (3 N + 20) dB with a minimum of 38dB were N is the constellation size of a carrier (in bits).
An analog multiplexer allows the selection between two input ports which can be used to select an attenuated(0, 10dB for ex.) version of the signal in case of short loop or large echo. The signal is amplified by a low noise gain stage (031dB) then low-pass filtered to avoid anti-aliasing and to ease further digital processing by removing unwanted high frequency out-of-band noise. A 12-bit A/D converter samples the data at 8.832MS/s (or 4.416MS/s in alternative mode), transforms the signal into a digital representation and sends it to the DMT signal processor via the digital interface. The Transmitter (TX) part The 12-bit data words at 8.832MS/s (or 4.416MS/s) coming from the DMT signal processor through the digital interface are transformed by D/A converter into a analog signal. This signal is then filtered to decrease DMT sidelobes level and meet the ANSI transmitter spectral response but also to reduce the out-of-band noise (which can be echoed to the RX path) to an acceptable level. The pre-driver buffers the signal for the external line driver and in case of short loop provide attenuation (-15...0dB). The VCXO part The VCXO is divided in a XTAL driver and a auxiliary 8 bits DAC for timing recovery. The XTAL driver is able to operate at 35.328MHz and provides an amplitude regulation mechanism to avoid temperature / supply / technology de2/22
STLC60134S
Maximum / minimum signal levels The following table gives the transmitted and received signal levels for both ATU-R and ATU-C sides. All the levels are referred to the line voltages (i.e. after hybrid and transformers in TX direction, before hybrid and transformer in RX direction). Note that signal amplitudes shown below are for illustration purpose and depending on the transTable 1. Target Signal Levels (on the line).
Parameter RX Max level Max RMS level Min level Min RMS level 839 mVpdif 168 mVrms 54 mVpdif 11 mVrms ATU - C TX 15.8 Vpdif 3.16 Vrms 3.95 Vpdif 791 mVrms RX 3.95 Vpdif 791 mVrms 42 mVpdif 8 mVrms 3.4 Vpdif 671 mVrms 839 mVpdif 168 mVrms ATU - R TX
mit power and line impedance signal amplitudes can differ from these values. The reference line impedance for all power calculations is 100. PACKAGE The STLC60134S is packaged in a 64-pin TQFP package (body size 10x10mm, pitch 0.5mm).
Table 2. Total Signal Level (on the line).
Parameter RX Max level for receiver 4 Vpdif (Long line) ATU - C TX RX 4.2 Vpdif (Short line) ATU - R TX
Figure 2. Pin Connection
AVDD1 AVDD2 XTALO DVSS2 AVSS1 AVSS2 AVSS6 RXIN1 RXIP1 VCXO XTALI IVCO IREF RES TX2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RES GP0 DVDD2 AVSS3 VRAN VRAP VREF LTNT AVDD3 PDOWN RESETN AVDD4 NC0 NC1 TXN TXP TX3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TX1 TX0 NU3 NU2 NU1 NU0 CTRLIN DVSS1 CLKM CLNIB CLWD RX3 RX2 RX1 RX0 DVDD1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RXIP0 RXIN0 GC1 GC0 VCOC GP2 AVDD6 AVDD5 RES RES AGND RES RES AVSS5 AVSS4 GP1
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STLC60134S
Table 3. Pin Functions.
N. 24 25 26 31 32 38 44 45 46 47 48 49 50 53 55 56 59 60 1 2 7 9 10 11 12 13 14 15 18 19 20 22 33 43 63 64 21 36, 37, 39, 40, 57 8 16 17 23 27 4/22 Name VRAP VREF VRAN TXP TXN AGND VCOC GC0 GC1 RXN0 RXP0 RXN1 RXP1 IREF IVCO VCXO XTALI XTALO TX1 TX0 CTRLIN CLKM CLNIB CLWD RX3 RX2 RX1 RX0 PDOWN LTNT RESETN GP0 GP1 GP2 TX3 TX2 RES RES Function positive voltage reference ADC ground reference ADC negative voltage reference ADC pre driver output pre driver output virtual analog ground (AVDD/2 = 1.65V) VCODAC time constant capacitor External gain control output LSB External gain control output MSB analog receive negative input Gain 0 analog receive positive input Gain 0 analog receive negative input Gain 1 (most sensitive input) analog receive positive input Gain 1 (most sensitive input) current reference TX DAC/DACE current reference VCO DAC VXCO control current XTAL oscillator input pin XTAL oscillator output pin PCB connection Decoupling network Decoupling network Decoupling network Line driver input Line driver input Decoupling network VCODAC cap. Supply
ANALOG INTERFACE
AVDD3 AVDD3 AVDD3 AVDD4 AVDD4 AVDD5 AVDD5 AVDD5 AVDD5 Echo filter output AVDD5 Echo filter output AVDD5 Echo filter output AVDD5 Echo filter output AVDD5 Decoupling network AVDD2 VCO bias network AVDD1 VCXO filter AVDD1 Crystal + varicap AVDD1 Crystal + varicap AVDD1 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 DVDD2 AVDD AVDD AVDD DVDD2 DVDD2
DIGITAL INTERFACE
digital transmit input, parallel data digital transmit input, parallel data serial data input (settings) Async Interface master clock output, f = 35.328MHz Load = CL<30pF nibble clock output, f = 17.664MHz (OSR = 2) or ground (OSR = 4) Load = CL<30pF word clock output, f = 8.832/4.416MHz Load = CL<30pF digital receive output, parallel data Load = CL<30pF digital receive output, parallel data Load = CL<30pF digital receive output, parallel data Load = CL<30pF digital receive output, parallel data Load = CL<30pF power down select, "1" = power down Power down input ATU-R / ATU-C select pin 1, ATU-R = 0 /ATU-C = 1 / test VDD in ATU-C mode mode MSB reset pin (active low) RC- reset General purpose output 0 (on AVDD 1) Echo filter output General purpose output 1 (on AVDD 1) Echo filter output General purpose output 2 (on AVDD 1) Echo filter output digital transmit input, parallel data Load = CL<30pF digital transmit input, parallel data Load = CL<30pF RESERVED Must be connected to DVSS (input) Must be connected RESERVED to AVSS (input)
SUPPLY VOLTAGES
DVSS1 DVDD1 DVDD2 AVSS3 AVDD3 Digital I/O supply voltage digital internal supply voltage ADC supply voltage DVSS DVDD DVDD AVSS AVDD
STLC60134S
Table 3. Pin Functions (continued)
28 34 35 41 42 51 52 54 58 61 62 SPARES 3 4 5 6 29 30
1
AVDD4 AVSS4 AVSS5 AVDD5 AVDD6 AVSS6 AVSS2 AVDD2 AVDD1 AVSS1 DVSS2 NU3 NU2 NU1 NU0 NC0 NC1
TX pre - drivers supply
CT filter supply LNA supply
DAC and support circuit XTAL oscillator supply voltage
AVDD AVSS AVSS AVDD AVDD AVSS AVSS AVDD AVDD AVSS DVSS DVSS DVSS DVSS DVSS
Not Not Not Not
used inputs used inputs used inputs used inputs
LT AUT-C; NT ATU-R
Figure 3. Grounding and Decoupling Networks.
VRAP pin
10F
VRAN pin ANALOG VDD
4.7H L1 10F 100nF
10F
100nF
10F
100nF
AVDD (each pin must have its own capacitor) 100nF
VREF pin 10F 100nF
IREF pin 100nF
VCOC pin 10F 100nF 10F
AGND pin
D98TL356
ATU-C END: BLOCK DIAGRAM The transformer at ATU-C side has 1:2 ratio. The termination resistors are 12.5 in case of 100 lines. The hybrid bridge resistors should be < 2.5k for low-noise. An HP filter must be used on the TX path to re-
duce DMT sidelobes and out of band noise influence on the receiver. On the RX path, a LP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce crosstalk between STLC60134S signals and POTS speech and signalling.
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Figure 4. ATU-C END Block Diagram.
POTS 35.328MHz LINE Zo=100 LP POTS FILTER MASTER CLOCK 35.328MHz XTRAL DRIVER RXT2 R R RXP(0:1) 0..31dB 4 12.5 12.5 GRX LPF LNA LP138KHz SC2 12-bit A/D CONVERTER CTRLIN LTNT=1 RESETN TO STLC60135 NIBBLES 17.664MHz WORD 8.832/4.416MHz RXn 8.832MS/s 4.416MS/s
2:1 HP POTS FILTER RXT1
RXN(0:1) 2R 2R
GTX LINE DRIVER HPF
-15..0dB TXP 4 PD TXN LP 1.1MHz HC2 12-bit D/A CONVERTER TXn 8.832MS/s 4.416MS/s
D98TL357mod
ATU-R END: BLOCK DIAGRAM The ATU-R side block diagram is equal to the ATU-C side block diagram with the following differences: - The transformer ratio is 1:1 - Termination resistors are 50 for 100 lines. An LP filter may be used on the TX path to reFigure 5. ATU-R END Block Diagram.
POTS
duce DMT sidelobes and out of band noise influence on the receiver. On the RX path, a HP filter must be used in order to reduce the echo signal level and to avoid saturation of the input stage of the receiver. The POTS filter is used in both directions to reduce crosstalk between ADSL signals and POTS speech and signalling. Low pass POTS filter can be very simple for Lite - ADSL application
35.328 MHz LINE Zo=100 1:1 VCODAC HP POTS FILTER RXT1 R R RXT2 RXP(0:1) 0. .31dB 4 50 50 GRX HPF LNA LP 1.1MHz HC2 12- bit A/D CONVERTER CTRLIN LTNT=0 RESETN TO STLC60135 RXn 8.832MS/s 4.416MS/s LP POTSFILTER VCXOUT MASTER CLOCK 35.328MHz XTAL DRIVER NIBBLES 17.664MHz WORD 8.832/4.416MHz
RXN(0:1) 2R 2R
GTX LI NE DRIVER LPF
-15..0dB TXP 4 PD TXN
D98TL358mod
LP 138KHz SC2
12-bit D/A CONVERTER
TXn 8.832MS/s 4.416MS/s
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RX PATH Speech filter An external bi-directional LC filter for up and downstream POTS service splits the speech signal from the ADSL signal to the POTS circuits on ATU-C. The ADSL analog front end integrated circuit does not contain any circuitry for the POTS service but it guarantees that bandwidth is not disturbed by spurious signals from the ADSL-spectrum. Channel Filters The external analog circuits provide partial echo cancellation by an analog filtering of the receive signal for both ATU-R (Reception of downstream channel) and ATU-C (Reception of upstream channel). This is feasible because the upstream and the downstream data can be modulated on separate carriers (FDM). Line Noise Model The power spectral density of the crosstalk noise sources as described in ANSI document is given in the figure below (no HDB3 interferer signals). Also given in dotted line, is the noise model used in this document to specify the sensivity requirements which are stronger than the original ones. Figure 6. Crosstalk PSD. AGC of RX path The AGC gain in the RX-path is controlled through a 5-bits digital code. Four inputs are provided for RX input and the selection is made with the RXMUX bits of the CTRLIN interface. This can be used to make lower gain paths in case of high input signal.
D98TL359
the frequency band of interest. The maximum noise density within the pass band can exceed the average value as follows: ATU-R RX path (max AGC setting): <100nVHz-1/2 @ 138kHz <31nVHz-1/2 for 250kHz < f ATU-C RX path (max AGC setting): <100nVHz-1/2 for 34.5kHz < f <138kHz RX-PATH NOISE AT MINIMUM GAIN At the minimum AGC the total average thermal noise of the analog RX-path at the ADC input should be lower than the ADC quantisation noise. The maximum noise density within the pass band can exceed the average value as follows: ATU-R RX path (min AGC setting): <500nVHz-1/2 @ 138kHz < f ATU-C RX path (min AGC setting): <1.5VHz-1/2 @ 34.5kHz < f < 138kHz These noise specifications correspond with 10bit resolution of the complete RX-path. Table 4. RX Common-mode Voltage
Description Common mode signal VCM at RXIN1 and RXIN2: Value/Unit 1.6V < VCM <1.7V
dBm/Hz -100 -110 -120 -130 -140 79.5 138 250 795 kHz
Table 5. AGC Characteristics.
Description Input referred noise (max. gain) Max. input level Max. output level Gain range Gain and step accuracy Value/Unit 20nVHz -1/2 1Vpd 1Vpd 0 to 31dB with step = 1dB 0.3dB
Signal to Noise Performance RX- PATH SENSITIVITY AT MAXIMUM GAIN The RX path sensitivity at the maximal RX-AGC of the ATU-R receiver is defined at -140dBm/Hz (for 100 ref) on the line. This figure corresponds to the equivalent input noise of 31nVHz-1/2 seen on the line. The sensitivity at the maximal RX - gain of the ATU-C receiver is defined at -130dBm/Hz (for 100 ref) on the line. The figure corresponds to the equivalent input noise of 100nVHz-1/2 seen on the line. Both noise figures include the noise of the hybrid. It is the equivalent average thermal noise over
RX Filters The combination of the external filter (an LC ladder filter typically) with the integrated lowpass filter must provide: - echo reduction to improve dynamic range - DMT sidelobe and out of band (anti-aliasing) attenuation. - Anti alias filter (60dB rejection @ image freq.)
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ATU-R RX Filters The integrated filter have the following characteristics: Table 6. Integrated HC Filter Characteristics
Description Input referred noise Max. input level Max. output level Type Frequency band Frequency tuning Max. in-band ripple Matlab Model Default cut off frequency @ -3dB Actual cut off @ -3dB HC Freq. selection register 100nVHz-1/2 1Vpd 1Vpd 3rd order butterworth 1.104MHz (0%setting, see below) -43.75% -> +0% 1dB [B, A] = butter (3, w0, 's') F0 = 1560KHz w0 = 2 * pi * F0/((20 + n)/16) n = -4,..,3 see (AFE settings ,Table 22) Value/Unit
Table 7. Phase Characteristic
Description Total RX filter group delay TotalRX filter group delay distortion Value/Unit < 50s @ 138kHz < f < 1.104MHz < 15s @ 138kHz < f < 1.104MHz
Figure 7. HC Filter Mask for ATU-R RX and ATU-C TX
AMPLITUTDE 0dB +/-1dB 5dB 36dB 50dB
30
D98TL360
1104 2208
7728
16560
kHz
Note: The total ATU_R RX path (including ADC) group delay distortion is 16s (i.e. = 15s + 1s of ADC)
ATU-C RX filter This filter is the same as the one used for ATU-R TX. Linearity of RX Linearity of the RX analog path is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5Vpd amplitude (total 1Vpd) at the output of the RX - AGC amplifier (i.e: before the ADC) for the case of minimal AGC setting. The following tables 8 and 9 list the RX path intermodulation distortion (as S/IM3 ratio) in downstream and upstream bandwidth. Table 8. Linearity of ATU-R RX
f1 (0.5Vpd) f2 (0.5Vpd) S/IM3 (AGC = 0dB) 300kHz 200kHz 59.5dB @ 53.5dB @ 43.5dB @ 42.5dB @ 100kHz 400kHz 700kHz 800kHz 500kHz 400kHz 59.5dB @ 300kHz 48.0dB @ 600kHz 700kHz 600kHz 48.0dB @ 500kHz 42.5dB @ 800kHz
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Table 9. Linearity of ATU-C RX
f1 (0.5Vpd) f2 (0.5Vpd) S/IM3 (AGC = 20 dB) 80kHz 70kHz 56.5dB @ 60kHz 56.5dB @ 90kHz
2f2 - f1 2f1 - f2
Table 10. RX Filter to A/D Interface
RX filter to A/D maximal level: 1Vpd = full scale of A/D
Table 11. A/D Convertors (A pipeline architecture is used for A/D convertors).
Numbers of bits: Minimum resolution of the A/D convertor Linearity error of the A/D convertor Full scale input range: Sampling rate: Maximum attenuation at 1.1MHz: Maximum group delay: Maximum group delay distortion: 12bits 11bits <1LSB (out of 12bits) 1 Vpdif 5% 8.832MHz (or 4.416MHz in OSR = 2 mode) <0.5dB without in-band ripple <3s <1s
Power Supply Rejection The noise on the power supplies for the RX path must be lower than the following: <50mVrms in band white noise for any AVDD. In this case, PSR (power supply rejection) of STLC60134S RX path is lower than -43dB. TX PATH Transmitter Spectral Response The two figures below show the ANSI spectral response mask for ATU-C and ATU-R transmitters Figure 8. ATU-C TX spectral response mask
dBm/Hz -40 +/-3dB 24dB 50dB
-64
-90 30
D98TL361
1104 2208
11040
KHz
Figure 9. ATU-R TX spectral response mask
dBm/Hz -40 +/-3dB 24dB 48dB
-64
-88 30
D98TL362
138
181
224
KHz
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Table 12. AGC of TX Path (from filter output to TXP and TXN).
Output noise Input level (nominal) Output level nominal, full-scale Maximum Output Load AGC range: AGC step: Gain and step accuracy 25mVHz-1/2 1Vpd 1.5Vpd > 500; <10pF -15dB...dB 1dB 0.3dB
Minimum code (0000) stands for AGC = -15dB and maximum (1111 - MSB left) for AGC = 0dB (See Tx setting, Table22). TX Pre-driver Capability The pre-driver drives an external line power amplifier which transmits the required power to the line. Table 13. TX Pre-driver
TX drive level to the external line driver for max. AGC setting External line driver input impedance: Pre-driver characteristics: closed loop gain: ooutput impedance: output offset voltage (0dB) input noise voltage (0dB) < 10mV < 20nVHz-1/2 @ f > 250k < 50nVHz-1/2 @ 34.5K < f <138k 1.6V < Vcm < 1.7V -15dB...0dB with step = 1dB resistive capacitive 1.5 Vpdif > 500 < 30pF
output common mode voltage:
TX Filter The TX filters act not only to suppress the DMT sidebands but also as smoothing filters on the D/A convertor's output to suppress the image spectrum. For this reason they must be realized in a continuous time approach. ATU-R TX Filter The purpose of this filter is to remove out-of-band noise of the ATU-R TX path echoed to the ATU-R RX path. In order to meet the transmitter spectral response, an additional filtering must be (digitally) performed. The integrated filter has the following characteristics: Table 14. Integrated SC Filter Characteristics
Description Input referred noise Max. input level Max. output level Type Frequency band Frequency tuning Max. in-band ripple Matlab Model Default cut-off frequency @ -3dB Actual cut-off @ -3dB SC Freq. selection register 100nVHz 1Vpd 1Vpd 4th order chebytchef 138kHz (0% setting see below) -25% -> +25% 1dB [B,A] = cheby1 (4,0.5,W0,'s') {ripple = 0.5} F0 = 151.8kHz W0 = 2*pi*F0/((17+n)/16) n = -4,..,3 see (AFE settings, Table 22)
-1/2
Value/Unit
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Table 15. Phase characteristics
Description Total TX filter group delay Total TX filter group delay distortion Value/Unit <50s @ 34.5kHz < f < 138kHz <20s @ 34.5kHz < f < 138kHz
Note: The total ATU-R TX path (including DAC) group delay distortion is 16s (i.e. = 15s + 1s of DAC)
Figure 10. SC Filter Mask for ATU-CRX and ATU-R TX
AMPLITUTDE 0dB +/-1dB 20dB
30
D98TL363
138
250
KHz
Table 16. D/A Convertor (A current steering architecture is used).
Description Numbers of bits: Minimum resolution of the D/A convertors Linearity error of the A/D convertor Full scale input range: Sampling rate: Maximum group delay: Maximum group delay distortion: 12bits 11bits <1LSB (out of 12bits) 1 Vpdif 5% 8.832MHz (or 4.416MHz in compatible mode) <3s <1s Value/Unit
Linearity of ATU-C TX Linearity of the TX is defined by the IM3 product of two sinusoidal signals with frequencies f1 and f2 and each with 0.5Vpd amplitude (total 1Vpd) at the output of the pre-driver for the case of a total AGC = 0dB. Table 17. Linearity of ATU-C TX
f1 (0.5Vpd) f2 (0.5Vpd) S/IM3 (AGC = 0dB) 300kHz 200kHz 59.5dB @ 100kHz 53.5dB @ 400kHz 43.5dB @ 700kHz 42.5dB @ 800kHz 500kHz 400kHz 59.5dB @ 300kHz 48.0dB @ 600kHz 700kHz 600kHz 48.0dB @ 500kHz 42.5dB @ 800kHz
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Linearity of ATU-R TX Table 18. Linearity of ATU-R TX
f1 (0.5Vpd) f2 (0.5Vpd) S/IM3 (AGC = 0 dB) 80kHz 70kHz 59.5dB (@ 60KHz, 90KHz)
TX IDLE CHANNEL NOISE ATU-C TX idle channel noise The idle channel noise specifications correspond with 11bit resolution of the complete TX-path. ATU-C TX idle channel output noise on TX. Table 19. ATU-C TX idle channel noise
For max AGC setting (0dB) In-band noise Out-of-band noise For min AGC setting (=-15dB) In-band noise 500nVHz-1/2 500nVHz-1/2 80nVHz
-1/2
@ 138kHz -1.104MHz @ 34.5kHz -138kHz @ 138kHz -1.104MHz
ATU-R TX idle channel noise ATU-R TX idle channel output noise on TXP, TXN Table 20. ATU-R TX idle channel noise
For max AGC setting (0dB) In-band noise Out-of-band noise For min AGC setting (=-15dB) In-band noise 500nVHz-1/2 @ 34kHz -138kHz 1.6VHz-1/2 -1/2 1.6VHz 150nVHz-1/2 @ 34.5kHz -138kHz @ 138kHz @ 250kHz -1.104MHz
Power Supply Rejection The noise on the power supplies for the TX-path must be lower than the following: < 50mVrms in-band white noise for AVDD. < 15mVrms in-band white noise for Pre-driver AVDD. VCXO A voltage controlled crystal oscillator driver is integrated in STLC60134S. The nominal frequency is 35.328MHz. The quartz crystal is connected between the pins XTALI and XTALO. The principle of the VCXO control is shown in figure 11. The information coming from the digital processor via the CTRLIN path is used to drive an 8-bit DAC which generates a control current. This current is externally converted and filtered to generate the required control voltage (range:-15V to 0.5V) for the varicap. The VCXO circuit characteristics are given in Table 21.
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Table 21. VCXO circuit Characteristics
Symbol fabs frange IO Ii Parameter Absolute frequency accuracy Frequency Tuning Range VCXO Output Current Reference Input Current Min. -15ppm Nominal 35.328MHz 50ppm 100A Max. +15ppm Note
100A
1mA
Rref = 16.5k AVDD = 3.3V AVDD = 3.3V
N.B: frequency tuning range is proportional to the crystal dynamic capacitance Cm.
Figure 11. Principle of VCXO control
AVDD CS VCOCX AVDD/22/AVDD/2 IVCO Ii RREF AVDD
1M 8 bits CTRLIN DAC 30%
IO=Ii Filtered VCXO (se e CTRLIN table) Clk35 VCXOUT AGND XTALO CP Ct Rt
-15V XTALI
D98TL364mod
The tuning must be monotonic with 8-bit resolution with the worst-case tuning step of <2ppm/LSB (8-bit). The time constant of the tuning must be variable from 5s to 10s through an external capacitor Cs (R = 1M 30%). This determines the speed of the VCXO in normal operation (slow speed in "show time") with filtered VCXO. For faster tracking, the previous filter is not used and the speed depends on CtRt.
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DIGITAL INTERFACE Control Interface The digital setting codes for the STLC60134S configuration are sent over a serial line (CTRLIN) using the word clock (CLWD). The data burst is composed of 16 bits from which the first bit is used as start bit ('0'), the three LSBs being used to identify the data contained in the 12 remaining bits. Test related data are overruled by the normal settings if the TEST pin is low. Table 22. Control Interface Bit Mapping
M S B b 1 5 0 0 0 0 0 0 0 0 0 0 0 0 b 1 5 0 0 0 0 0 0 0 0 0 b 1 5 0 0 0 0 0 0 0 0 L S B b 0 0 0 0 0 0 0 0 0 0 0 0 0 b 0 1 1 1 1 1 1 1 1 1 b 0 0 0 0 0 0 0 0 0
b 1 4 x
b 1 3 x
b 1 2
b 1 1
b 1 0
b 9
b 8
b 7
b 6
b 5
b 4
b 3
b 2 0 0 0 0 0 0 0 0 0 0 0 0 b 2 0 0 0 0 0 0 0 0 0 b 2 0 0 0 0 0 0 0 0
b 1 0 0 0 0 0 0 0 0 0 0 0 0 b 1 0 0 0 0 0 0 0 0 0 b 1 1 1 1 1 1 1 1 1
RX SETTINGS
0 1 0 0 x 1 0 0 x 1 0 0 x 1 0 0 x 1 0 1 x 1 0 0 1 1 b 6 0 1 0 1 b 5
External Gain Control GC1 (init = 0) External Gain Control GC0 (init = 0) Rx input selected = RXIN0, RXIP0 (init) Rx input selected = RXIN1, RXIP1 AGC RX Gain setting 0dB (init) AGC RX Gain setting 1dB AGC RX Gain setting XdB AGC RX Gain setting 31dB Normal mode Filter selection see LTNT pin (init) In ATU-C conf, force HC2 for RX path, TX grounded In ATU-C conf, force HC1 for RX path Normal mode Filter selection see LTNT pin TX SETTINGS Transmit TX - AGC setting -15dB Transmit TX - AGC setting -14dB Transmit TX - AGC setting (X - 15) dB Transmit TX - AGC setting 0dB Not used Not used Not used Not used General Purpose Output (GPO) setting AFE SETTINGS Normal Mode (Digital path) (init) Digital Loopback (digital TX to digital RX - DAC not used) Normal Mode (Analog path) Analog loopback (RXi to TXi - ADC not used) 1) (init) VCO DAC disabled VCO DAC enabled (init) HC filter enabled (init) HC filter enabled (init)
b 1 4 0 0 x 1
b 1 3 0 0 x 1
b 1 2 0 0 x 1
b 1 1 0 1 x 1
b 1 0
b 9
b 8
b 7
b 4
b 3
0 0 0 0 b 1 4 0 1 b 1 3 b 1 2 b 1 1 b 1 0
0 0 0 0 b 9
0 0 0 0 b 8
0 0 0 0 b 7 x b 6 x b 5 x b 4 b 3
(init) (init) (init) (init) (init = 000)
0 1 0 1 0 1
1) After initialization, this bit has to be cleared (0) to make the device properly operate.
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STLC60134S
Table 22. Control Interface Bit Mapping (continued)
b 1 5 0 0 0 0 0 0 0 0 0 b 1 5 0 0 0 b 1 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 1 5 0 0 0 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 0 1 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 0 0 0 0 0 0 0 0 0 b 2 0 0 0 b 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b 2 1 1 1 b 1 1 1 1 1 1 1 1 1 1 b 1 1 1 1 b 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 1 0 1 1 b 0 0 0 0 0 0 0 0 0 0 b 0 1 1 1 b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b 0 1 0 1 AFE SETTINGS OSR set to 4 OSR set to 2 SC freq. selection: Fc = 138kHz SC freq. selection: Fc ~ 110kHz SC freq. selection: Fc ~ 170kHz HC freq. selection: Fc = 1.104MHz HC freq. selection: Fc ~ 768kHz VCXO output NOT filtered ("show-time") VCXO output filtered VCO DAC VALUE SETTINGS VCO DAC CURRENT value @ MINIMUM VCO DAC CURRENT value @ X VCO DAC CURRENT value @ MAXIMUM POWER DOWN ANALOG BLOCK SETTINGS TXD Active TXD in powerdown N.U. N.U. ADC Active ADC in powerdown HFC2 Active HFC2 in powerdown HFC1 Active HFC1 in powerdown SCF2 Active SCF2 in powerdown SCF1 Active SCF1 in powerdown LNA Active LNA in powerdown DAC Active DAC in powerdown DACE Active DACE in powerdown VCODAC Active VCODAC in powerdown XTAL Active XTAL in powerdown RESERVED RESERVED RESERVED RESERVED (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (init) (*) (*) (*) (init) (*) (*) (init)
1 0 1
1 1 0
1 1 1 1 0 0 1 0 1 0 1 b 3
b 1 4 0 x 1 b 1 4 0 1
b 1 3 0 x 1 b 1 3
b 1 2 0 x 1 b 1 2
b 1 1 0 x 1 b 1 1
b 1 0 0 x 1 b 1 0
b 9 0 x 1 b 9
b 8 0 x 1 b 8
b 7 0 x 1 b 7
b 6
b 5
b 4
b 6
b 5
b 4
b 3
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 b 3 x x x
b 1 4 x x x
b 1 3 x x x
b 1 2 x x x
b 1 1 x x x
b 1 0 x x x
b 9 x x x
b 8 x x x
b 7 x x x
b 6 x x x
b 5 x x x
b 4 x x x
(*) For each filter, 8 possible frequency values (see table 6 and table 14). Notation is 2's complement range from -4 = 100b +3 = 011b. Fc is the frequency band (-1dB)
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STLC60134S
Control Interface Timing The word clock (CLWD) is used to sample at negative going edge the control information. The start bit b15 is transmitted first followed by bits b[14:0] and at least 16 stop bits need to be provided to validate the data.
Figure 12. Control Interface.
CLWD
CTRLIN
START BIT
D98TL365
DATA ID.
>=16 STOP BITS=HIGH
Data set-up and hold time versus falling edge CLWD must be greater than 10nsec. Receive / Transmit Interface RECEIVE / TRANSMIT PROTOCOL The digital interface is based on 4 x 8.832MHz (35.328MHz) data lines in the following manner: If OSR = 2 (OSR bit set to 1) is selected, CLKNIB is used as nibble clock (17.664MHz, disabled in normal mode), and all the RXi, TXi, CLKWD periods are twice as long as in normal mode. This ensures a compatibility with lower speed products. TX Signal Dynamic The dynamic of data signal for both TX DACs is 12 bits extracted from the available signed 16 bit representationcoming from the digital processor. The maximal positive number is 214-1, the most negative number is -214, the 3 LSBs are filled with '0'. Any signal exceeding these limits is clamped to the maximum value. Table 23.
BIT MAP/NIBBLE TXD0 TXD1 TXD2 TXD3 N0 not used not used not used d0 = data bit 0 (LSB) N1 data bit 1 data bit 2 data bit 3 data bit 4 N2 data bit 5 data bit 6 data bit 7 data bit 8 N3 data bit 9 data bit 10 data SIGN data SIGN
Table 24. TX bit map
N3 sign sign d10 d9 d8 d7 N2 d6 d5 d4 d3 N1 d2 d1 d0 n.u. N0 n.u. n.u.
The two sign bits must be identical.
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STLC60134S
RX Signal Dynamic The dynamic of the signal from the ADC is limited to 13bits. Those bits are converted to a signed (2's complement) representation with a maximal positive number of 214 -1 and a most negative number -214. The 2 LSBs are filled with '0'. Table 25.
BIT MAP/NIBBLE RXD0 RXD1 RXD2 RXD3 N0 0 0 d0 = data bit 0 (LSB) data bit 1 N1 data bit 2 data bit 3 data bit 4 data bit 5 N2 data bit 6 data bit 7 data bit 8 data bit 9 N3 data bit 10 data bit 11 data SIGN data SIGN
Table 26. RX bit map
N3 sign sign d11 d10 d9 d8 N2 d7 d6 d5 d4 N1 d3 d2 d1 d0 N0 0 0
The two sign bits must be identical.
Figure 13. TX/ RX Digital Interface Timing
CLKM 35.328MHz CLWD 8.832MHz
TXDx/RXDx
N0 N1 N2 N3 OSR=4
CLKNIB 17.664MHz CLWD 4.416MHz
TXDx/RXDx
N0
D98TL366
N1 OSR=2
N2
N3
Receive / Transmit interface timing The interface is a triple (RX, TX) nibble - serial interface running at 8.8MHz sampling (normal mode). The data are represented in 16bits format, and transferred in groups of 4 bits (nibbles). The LSBs are transferred first. The STLC60134S generates a nibble clock (CLKM master clock in normal mode, CLKNIB in OSR = 2 mode) and word signals shared by the three interfaces. Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the falling edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital processor. Data, CLWD setup and hold times are 5ns with reference to the falling edge of CLKM/CLKNIB. (not floating).
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STLC60134S
Data is transmitted on the rising edge of the master clock (CLKM/CLKNIB) and sampled on the low going edge of CLKM/CLKNIB. This holds for the data stream from STLC60134S and from the digital processor. Data,CLWD setup and hold times are 5ns with reference to thefalling edgeof CLKM/CLKNIB. (not floating). POWER DOWN When pin Pdown = "1", the chip is set in power down mode. As the Pdown signal is synchronously sampled, minimum duration is 2 periods of the 35MHz clock. In this mode all analog functional blocks are deactivated except: preamplifiers (TX), clock circuits for output clock CLKM. Pdown will not affect the digital part of the chip. Anyway, after a Pdown transition, the digital part status, is updated after 3 clock periods (worst case) The chip is activated when Pdown = "0". In power down mode the following conditions hold: - Output voltages at TXP/TXN = AGND - Preamplifier is on with maximum gain setting (0dB), (digitalgain setting coefficients are overruled) - The XTAL outputclock on pin CLKM keepsrunning. - All digital setting are retained. - Digital output on pins RXDx don't care (not floating). In power-down mode the power consumption is 100mW. Following external conditions are added: - Clock pin CLW is running. - CTRLIN signals can still be allowed. - AGND remains at AVDD/2 (circuit is powered up) - Input signal at TXDx inputs are not strobed. The Pdown signal controls asynchronously the power-down of each analog module: - After a few s the analog channel is functional - After about 100ms the analog channel delivers full performance RESET FUNCTION The reset function is implied when the RESETN pin is at a low voltage input level. In this condition, the reset function can be easily used for power up reset conditions. Detailed Description During reset: (reset is asynchronous, tenths of ns are enough to put the IC in reset) All clock outputs are deactivatedand put to logical "1" (except for the XTAL and master clock CLKM) After reset: (4 clock periods after reset transition, as worst case) - OSR = 4 - All analog gains (RX, TX) are set to minimum value - Nominal filter frequency bands(138kHz, 1.104Hz) - LNA input = "11" (max. attenuation) - VCO dac disabled - Depending of the LTNT pin value the following configuration is chosen: '0' (ATU-R)
RX: TX: LNA -> HC2 -> ADC DAC -> SC2 -> TX
'1' (ATU-C)
RX: TX: 18/22 LNA -> SC2 -> ADC DAC -> HC2 -> TX
STLC60134S
Digital outputs are placed in don't care condition (non-floating). N.B. If a Xtal oscillator is used, the RESET must be released at last 10s after power-on, to ensure a correct duty cycle for the clk35 clock signal.
ELECTRICAL RATINGS AND CHARACTERISTICS Table 27. Absolute Maximum Ratings
Symbol VDD Vin Tstg TL ILU IAVDD IAVDD IDVDD IDVDD Parameter Any VDD Supply Voltage, related to substrate Voltage at any input pin Storage Temperature Lead Temperature (10 second soldering) Latch - up current @80C Analog Supply Current @ 3.6V - normal operation Analog Supply Current @ 3.6V - power down Analog Supply Current @ 3.6V - normal operation Analog Supply Current @ 3.6V - power down 100 165 30 56 50 Min - 0.5 -0.5 -40 Max 5 VDD +0.5 125 300 Unit V V C C mA mA mA mA mA
Table 28. Thermal Data
Symbol Rth j-amb Parameter Thermal and Junction ambient Value 50 Unit C/W
Table 29. Operating Conditions (Unless specified, the characteristic limits of 'Static Characteristics' in this document apply over an Top = -40 to 80 C; VDD within the range 3 to 3.6V ref. to substrate.
Symbol AVDD DVDD Vin /Vout Pd Tamb Tj Parameter AVDD Supply Voltage, related to substrate DVDD Supply Voltage, related to substrate Voltage at any input and output pin Power Dissipation Ambient Temperature Junction Temperature Min 3.0 2.7 0 0.4 -40 -40 Max 3.6 3.6 VDD 0.6 80 110 Unit V V V W C C
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STLC60134S
STATIC CHARACTERISTICS Table 30. Digital Inputs Schmitt-trigger inputs: TXi, CTRLIN, PDOWN, LTNT, RESETN, TEST
Symbol V IL VIH VH C imp Parameter Low Level Input Voltage High Level Input Voltage Hysteresis Input Capacitance 0.7 DVDD 1.0 1.3 3 Test Condition Min. Typ. Max. 0.3 DVDD Unit V V V pF
Table 31. Digital Outputs Hard Driven Outputs: RXi
Symbol V OL VOH Cload Parameter Low Level Output Voltage High Level Output Voltage Load Capacitance Test Condition Iout = -4mA Iout = 4mA 0.85 DVDD 30 Min. Typ. Max. 0.15 DVDD Unit V V pF
Clock Driver Output: CLKM, CLNIB, CLKWD
Symbol V OL VOH Cload DC Parameter Low Level Output Voltage High Level Output Voltage Load Capacitance Duty Cycle 45 Test Condition Iout = -4mA Iout = 4mA 0.85 DVDD 30 55 Min. Typ. Max. 0.15 DVDD Unit V V pF %
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STLC60134S
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.40 0.05 1.35 0.18 0.12
mm TYP. MAX. 1.60 0.15 1.40 0.23 0.16 12.00 10.00 7.50 0.50 12.00 10.00 7.50 0.60 1.00 0.75 1.45 0.28 0.20 0.002 0.053 0.007 MIN.
inch TYP. MAX. 0.063 0.006 0.055 0.009 0.057 0.011
OUTLINE AND MECHANICAL DATA
0.0047 0.0063 0.0079 0.472 0.394 0.295 0.0197 0.472 0.394 0.295 0.0157 0.0236 0.0295 0.0393
0(min.), 7(max.)
TQFP64
D D1 A D3 A1 48 49 33 32
0.10mm Seating Plane
A2
B
E3
E1
64 1 e 16
17 C
L1
E
L
K
TQFP64
B
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STLC60134S
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